A goal of integrated circuit (IC) design has been a reduction in the area of the IC. In order to achieve this goal, a designer can use a shorter height cell architecture to reduce the scale of the constituent components of the IC. At the time, the designer will often prefer to utilize high-pin density Boolean cells in order to increase the functionality of a component. Additionally, another goal of IC design has been to achieve a higher integration of devices within the integrated circuit. These three developments: the reduction in area of the IC, the high-pin density Boolean cells, and the higher integration of devices, have often lead to congestion and routability problems in an IC design layout. Increased congestion and routability problems in turn increase in the number of design rule violations, thereby jeopardizing the functionality of the resulting physical IC.